RXIE=DISABLE, ABTOINTEN=DISABLE, ABEOINTEN=DISABLE, THREIE=DISABLE, RBRIE=DISABLE
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0).
| RBRIE | RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt. 0 (DISABLE): Disable. Disable the RDA interrupt. 1 (ENABLE): Enable. Enable the RDA interrupt. |
| THREIE | THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5]. 0 (DISABLE): Disable. Disable the THRE interrupt. 1 (ENABLE): Enable. Enable the THRE interrupt. |
| RXIE | RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. 0 (DISABLE): Disable. Disable the RX line status interrupts. 1 (ENABLE): Enable. Enable the RX line status interrupts. |
| RESERVED | Reserved |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| RESERVED | Reserved |
| ABEOINTEN | Enables the end of auto-baud interrupt. 0 (DISABLE): Disable. Disable end of auto-baud Interrupt. 1 (ENABLE): Enable. Enable end of auto-baud Interrupt. |
| ABTOINTEN | Enables the auto-baud time-out interrupt. 0 (DISABLE): Disable. Disable auto-baud time-out Interrupt. 1 (ENABLE): Enable. Enable auto-baud time-out Interrupt. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |